Imaging array and method for supporting automatic exposure control in a radiographic system

ABSTRACT

An imaging array with integrated circuitry for supporting automatic exposure control and a method for using such an imaging array are provided. One or more electrodes are disposed substantially parallel with at least a portion of the array of pixels forming the imaging array and provide capacitively coupling to at least one photodiode electrode.

BACKGROUND

The present invention relates to radiographic imaging systems using flatpanel imaging arrays, and in particular, to such systems havingautomatic exposure control (AEC) sensing capability.

Referring to FIG. 1, AEC is used in radiography to control the x-raydosage delivered to the receptor. Typically, a sensor, separate from theimage acquisition devise itself, is positioned in front of or behind thereceptor, and senses the x-ray exposure in real time. The AEC deviceprovides an output signal 1 in real time, usually in the form of ananalog voltage that is proportional to the total delivered x-rayexposure. This signal 1 is used by x-ray source to terminate theexposure when the signal 1 identifies the exposure as having reached apredefined threshold 2.

Ideally, it would be desirable to use the receptor itself to sense theexposure and provide the AEC signal in real time. However, using theactual image acquisition device itself is problematic for the reasonthat it is intended to capture the signal on a frame-by-frame basis, andnot in real time. For example, in flat panel digital radiography, theexposure is integrated on each pixel and then read out, typically, everyfew seconds. The x-ray beam duration is defined in tens of milliseconds,so real time in this context would require millisecond orsub-millisecond updates to the total AEC signal value.

Referring to FIG. 2, in addition to this problem of time scaling,traditional AEC detectors for radiography provide an AEC signal that isproportional to specific regions of the total image, e.g., typical AECsensing regions 3 a, 3 b, 3 c used for chest radiography.

Referring to FIG. 3, in a conventional flat panel digital radiographysystem, an x-ray source 4 irradiates a patient 5 with an x-ray beam 6.The radiation 6 a not blocked or absorbed by the patient 5 is receivedby the flat panel detector 7. Typically, an external AEC detector (notshown) associated with the flat panel detector 7 provides the AEC signal8, which is monitored by a controller 9 to provide an appropriate x-raycontrol signal 10 to terminate x-ray emissions when an exposure levelsufficient to create a diagnostically useful image has been achieved.While external AEC detectors generally work well, they add significantcost to the overall system. Further, at least two external AEC detectorsare often required since, unlike many flat panel detectors, they are notintended to move between table and chest stands, but are built into thex-ray table or chest stand.

SUMMARY

In accordance with the presently claimed invention, an imaging arraywith integrated circuitry for supporting automatic exposure control anda method for using such an imaging array are provided. One or moreelectrodes are disposed substantially parallel with at least a portionof the array of pixels forming the imaging array and providecapacitively coupling to at least one photodiode electrode.

In accordance with one embodiment of the presently claimed invention, animaging array with integrated circuitry for supporting automaticexposure control includes: a plurality of bias lines to convey a biasvoltage; a plurality of data lines to convey a plurality of datasignals; a plurality of address lines to convey a plurality of addresssignals; a plurality of pixels disposed among a plurality of rows and aplurality of columns, wherein each pixel includes a photodiode coupledto one of the plurality of bias lines and including first and secondphotodiode electrodes, a switch transistor including a first switchelectrode coupled to the first photodiode electrode, a second switchelectrode coupled to one of the plurality of data lines and a controlelectrode coupled to one of the plurality of address lines; and at leastone electrode disposed substantially parallel with at least one portionof the plurality of pixels and capacitively coupled to at least one thefirst photodiode electrode.

In accordance with another embodiment of the presently claimedinvention, a method of monitoring electrical charges accumulating withinan imaging array for supporting automatic exposure control includes:accumulating electrical charges within an imaging array that includes aplurality of bias lines to convey a bias voltage, a plurality of datalines to convey a plurality of data signals, a plurality of addresslines to convey a plurality of address signals, a plurality of pixelsdisposed among a plurality of rows and a plurality of columns, whereineach pixel includes a photodiode coupled to one of the plurality of biaslines and including first and second photodiode electrodes, a switchtransistor including a first switch electrode coupled to the firstphotodiode electrode, a second switch electrode coupled to one of theplurality of data lines and a control electrode coupled to one of theplurality of address lines; and capacitively coupling to at least onethe first photodiode electrode with at least one electrode disposedsubstantially parallel with at least one portion of the plurality ofpixels.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an output signal level versus exposure levelcharacteristic of an automatic exposure control signal.

FIG. 2 illustrates AEC sensing regions for chest radiography.

FIG. 3 depicts an x-ray system using a flat panel detector.

FIG. 4 depicts internal construction of an indirect flat panel detector.

FIG. 5 illustrates a plan view of a portion of a photodiode array.

FIG. 6 is a schematic diagram of a photodiode array.

FIG. 7 is a schematic diagram of a pixel and its associated readoutcircuitry.

FIG. 8 is a schematic diagram of a pixel and its associated readoutcircuitry including the parasitic capacitance of the pixel.

FIG. 9 depicts construction of a flat panel detector supporting AEC inaccordance with an exemplary embodiment of the presently claimedinvention.

FIG. 10 is a schematic diagram depicting the electrical connection of anAEC electrode in relation to a photodiode of a pixel.

FIG. 11 is a schematic diagram depicting addressing circuitry for anarray of AEC electrodes.

FIG. 12 depicts a radiography system using a flat panel detectorsupporting AEC in accordance with another exemplary embodiment of thepresently claimed invention.

DETAILED DESCRIPTION

The following detailed description is of example embodiments of thepresently claimed invention with references to the accompanyingdrawings. Such description is intended to be illustrative and notlimiting with respect to the scope of the present invention. Suchembodiments are described in sufficient detail to enable one of ordinaryskill in the art to practice the subject invention, and it will beunderstood that other embodiments may be practiced with some variationswithout departing from the spirit or scope of the subject invention.

Throughout the present disclosure, absent a clear indication to thecontrary from the context, it will be understood that individual circuitelements as described may be singular or plural in number. For example,the terms “circuit” and “circuitry” may include either a singlecomponent or a plurality of components, which are either active and/orpassive and are connected or otherwise coupled together (e.g., as one ormore integrated circuit chips) to provide the described function.Additionally, the term “signal” may refer to one or more currents, oneor more voltages, or a data signal. Within the drawings, like or relatedelements will have like or related alpha, numeric or alphanumericdesignators. Further, while the present invention has been discussed inthe context of implementations using discrete electronic circuitry(preferably in the form of one or more integrated circuit chips), thefunctions of any part of such circuitry may alternatively be implementedusing one or more appropriately programmed processors, depending uponthe signal frequencies or data rates to be processed. Moreover, to theextent that the figures illustrate diagrams of the functional blocks ofvarious embodiments, the functional blocks are not necessarilyindicative of the division between hardware circuitry. Thus, forexample, one or more of the functional blocks may be implemented in asingle piece of hardware.

As is well known, a flat panel detector 7 can be either an indirect flatpanel detector or a direct flat panel detector. As its well-known in theart, an indirect flat panel detector uses a scintillator screen toreceive the x-ray radiation and generate visible photons, which are, inturn, captured and converted to electron-hole pairs in a photodiodearray. This is contrast to a direct flat panel detector that convertsthe x-ray photon energy directly to electron-hole pairs.

Referring to FIG. 4, a conventional indirect flat panel detectorincludes the scintillator screen 11, a pixel array 12, a base plate 13,digital circuitry 14, driver circuitry 15 and readout circuitry 16, inaccordance with well-known principals and techniques. Typically, thecore of the flat panel detector 7 is an amorphous silicon (a-Si)photodiode array 12, which is fabricated on a glass substrate usingstandard semiconductor processing. While a number of pixel architecturesare in use, perhaps used most often is a p-i-n, thin film transistorarchitecture, in which each pixel includes a thin film transistor (TFT)and a p-i-n photodiode.

Referring to FIG. 5, each pixel 20 of such a photodiode array includesthe photodiode 22 and TFT Switch 24, which are connected to a bias line21, a data line 23 and a row, or address, line 25, in accordance withwell-known principals. The light sensitive p-i-n photodiode 22 occupiesmost of the surface area of the array. Its top electrode is typicallyindium tin oxide (ITO) and allows visible light to penetrate the diode.Further, the top side p-layer of the photodiode is made thin enough toallow most of the visible photons to be absorbed in the thickerintrinsic layer of the photodiode.

Referring to FIG. 6, electrical operation of such a photodiode array canbe understood in accordance with the circuit schematic as shown. Asdiscussed above, each pixel 20 includes a photodiode 22 and TFT switch24. The gate, or control, electrode of the TFT switch 24 is driven bythe row, or address, line 25. The anode of the photodiode 22 is biasedby a bias voltage 21 and the output electrode of the TFT switch 24drives the data line 23. The row, or address, lines 25 are driven bygate driver circuitry 15, and the data lines 23 provide data signals tothe readout circuitry 16, all in accordance with well-known principlesand techniques.

Referring to FIG. 7, operation and interaction between the photodiodearray 12 and readout circuitry 16 can be better understood. As discussedabove, a bias voltage source 30 provides a bias voltage 21 to the anodeof the photodiode 22. During an exposure, charges collect within thecapacitance of the photodiode, thereby generating a pixel voltage at thenode a connecting the photodiode cathode and TFT switch 24. The TFTswitch 24 is turned on and off by a control voltage 33 provided by aswitch control voltage source 32.

When the TFT switch 24 is turned on, the charges from the photodiode 22form a current which is converted to a voltage 35 by integrationcircuitry implemented using a differential amplifier 34 driven by areference voltage 47, and a feedback capacitance 36, in accordance withwell-known principles and techniques. The integrated voltage 35 isconveyed via a coupling capacitor 42 to a voltage amplifier 40, theoutput voltage 41 of which is sampled by a switch 44 and stored across acapacitance 46, in accordance with well-known principles and techniques.

At the pixel level readout timing is as follows. During integration, theTFT switch 24 is open, or off. Light absorbed by the photodiode 24creates electron-hole pairs in its intrinsic layer. The internal fieldof the photodiode under reverse bias separates the electrons and holes,forcing them to opposing electrodes, thereby causing charge to be storedon the capacitance formed in the photodiode. This charge stored on thepixel capacitance causes the voltage on the floating node a to move in anegative direction, thereby reducing the bias across the photodiode 22.

During readout, the TFT switch 24 is closed, or on, thereby connectingnode a of the pixel to the data line 23, which is held at a virtual biaspotential provided by the reference voltage 47 of the differentialamplifier 34. Node a is then discharged onto the data line 23 and intothe feedback capacitance 36 of the integration circuitry.

As depicted in the signal timing diagram portion, the feedbackcapacitance 36 is discharged by a reset switch 38 in accordance with areset control signal 39. This is followed by the TFT switch 24 beingturned on in accordance with its gate, or control, voltage 33 todischarge the pixel photodiode 22. This signal charge is accumulated onthe feedback capacitance 36 for conversion to a voltage 35, which, afterbuffering by the voltage amplifier 40, is sampled by a sampling switch44 in accordance with a sample control signal 45.

Referring to FIG. 8, in accordance with an exemplary embodiment of thepresently claimed invention, a parasitic effect present in the normaloperation of the flat panel when the x-ray beam is incident during thereadout of the frame time is used advantageously. For example, when apixel is integrating, the TFT switch 24 is turned off. The scintillatorlight hitting the photodiode 22 creates a photo-generated current in thediode 22. This causes the voltage at node a to move in a negativedirection. A parasitic capacitance 26 exists between node a and the dataline 23. As a result, the voltage movement at node a is sensed by thereadout amplifier 34 (when it is not in reset) due to the couplingeffect of the parasitic capacitance 26. Meanwhile, the data line voltage37 is held at a constant potential 47 due to the operation of thedifferential amplifier 34. As the voltage at node a changes, so does thevoltage across the parasitic capacitance 26. This means that a currentmust be supplied from the data line 23 to the parasitic capacitance 26so that the data line voltage 37 remains constant. During readout of thephotodiode array 12, every exposed pixel on a given data line 23contributes to this parasitic signal current.

The signals generated by this parasitic effect appear on acolumn-by-column basis with no row-dimension information. Accordingly,in accordance with an exemplarily embodiment of the presently claimedinvention, an additional layer is introduced on top of the photodiodearray where specific regions of this layer will be capacitively coupledto the photo-generated current within the photodiode array below.

Referring to FIG. 9, in accordance with an exemplary embodiment, such alayer is implemented in the form of a patterned ITO layer, e.g., withITO regions 50 a, 50 b, 50 c, on top of the final passivation layer 52to introduce the capacitor electrodes 50 a, 50 b, 50 c and theirconnections 51 a, 51 b, 51 c to the periphery of the array. These lines51 a, 51 b, 51 c can make a connection to TAB pads so that the capacitorelectrodes can be connected by a passive flex connection to readoutcircuitry similar to that forming the readout circuitry 16 as discussedabove for FIGS. 7 and 8.

This electrode layer 50 can be created during the array fabricationprocess, since ITO, dielectric and metal layers are available asstandard components both the fabrication process.

In accordance with another exemplary embodiment, the electrodes 50 canbe placed on the bottom of the ray, e.g., on the back side of itssupporting glass substrate. Advantages of these embodiment include: suchelectrodes can be metal (opaque); the electrodes are not screened fromthe active pixel node by other circuit components; the electrodes neednot be fabricated as part of the panel fabrication process, but can beapplied to the underside of the glass during the panel assembly process;and connection of the electrodes to circuit boards nearby may besimpler. However, sensitivity of the circuit may be degraded due to theincreased distance between the electrode and active pixel node, and theassembly process may require some manual handling.

Referring to FIG. 10, it can be seen schematically how the AECelectrodes 50 capacitively couple to an electrode, e.g., the cathode, ofthe photodiode 22.

Referring to FIG. 11, in accordance with another exemplary embodiment,the AEC electrodes 50 (FIGS. 9 and 10) can be implemented as an array ofsuch electrodes 50 a, 50 b, . . . , 50 n, with their signal lines 51 a,51 b, . . . , 51 n connected to interface circuitry 60 (e.g., addressingcircuitry in the form of multiplexors or switches), which can providefor addressing or accessing AEC signals from one or more desired regionsof interest in accordance with a programmable control signal 61. Theresulting selected signal 63 can then be further processed, e.g.,integrated by charge integration circuitry or amplified by amplifiercircuitry 62.

Referring to FIG. 12, the AEC signal voltage is traditionally an analogvoltage supplied to a threshold circuit that indicates to the radiationsource 4 when to terminate the x-ray pulse 6. Such an analog voltagecould be delivered from the flat panel display 57 as discussed above.However, in accordance with another exemplary embodiment, some flatpanel displays 57 provide what is referred to as an “Expose OK” signal58. This signal 58 is a binary signal that defines the “on” time inwhich the x-ray beam can be delivered to the panel 57. Generally, thiscorresponds to the integration phase of the panel read out cycle.Accordingly, this signal 58 also identifies the “off” state, thebeginning of which is when the accumulated AEC signal 51 measured in thepanel 57 has exceeded the predefined threshold. Accordingly, the “off”state of this signal 58 can be used to terminate the x-ray exposure.

Various other modifications and alternations in the structure and methodof operation of this invention will be apparent to those skilled in theart without departing from the scope and the spirit of the invention.Although the invention has been described in connection with specificpreferred embodiments, it should be understood that the invention asclaimed should not be unduly limited to such specific embodiments. It isintended that the following claims define the scope of the presentinvention and that structures and methods within the scope of theseclaims and their equivalents be covered thereby.

What is claimed is:
 1. An apparatus including an imaging array withintegrated circuitry for supporting automatic exposure control,comprising: a plurality of bias lines to convey a bias voltage; aplurality of data lines to convey a plurality of data signals; aplurality of address lines to convey a plurality of address signals; aplurality of pixels disposed among a plurality of rows and a pluralityof columns, wherein each pixel includes a photodiode coupled to one ofsaid plurality of bias lines and including first and second photodiodeelectrodes, a switch transistor including a first switch electrodecoupled to said first photodiode electrode, a second switch electrodecoupled to one of said plurality of data lines and a control electrodecoupled to one of said plurality of address lines; and at least oneelectrode disposed substantially parallel with at least one portion ofsaid plurality of pixels and capacitively coupled to at least one saidfirst photodiode electrode.
 2. The apparatus of claim 1, wherein said atleast one electrode comprises a plurality of planar conductors.
 3. Theapparatus of claim 1, wherein said at least one electrode comprises apatterned layer of electrically conductive material.
 4. The apparatus ofclaim 1, further comprising a layer of dielectric disposed over at leasta portion of said plurality of pixels, wherein said at least oneelectrode is disposed on at least a portion of said layer of dielectric.5. The apparatus of claim 1, further comprising a substrate disposedunder at least a portion of said plurality of pixels, wherein said atleast one electrode is disposed on at least a portion of said substrate.6. The apparatus of claim 1, wherein: said at least one electrodecomprises a plurality of electrodes disposed in an array; receivingcircuitry; and interface circuitry coupled between said plurality ofelectrodes and said receiving circuitry to selectively convey electricalcharges from one or more portions of said plurality of electrodes tosaid receiving circuitry.
 7. The apparatus of claim 1, furthercomprising amplifier circuitry coupled to said at least one electrode.8. The apparatus of claim 1, further comprising charge integrationcircuitry coupled to said at least one electrode.
 9. A method ofmonitoring electrical charges accumulating within an imaging array forsupporting automatic exposure control, comprising: accumulatingelectrical charges within an imaging array that includes a plurality ofbias lines to convey a bias voltage, a plurality of data lines to conveya plurality of data signals, a plurality of address lines to convey aplurality of address signals, a plurality of pixels disposed among aplurality of rows and a plurality of columns, wherein each pixelincludes a photodiode coupled to one of said plurality of bias lines andincluding first and second photodiode electrodes, a switch transistorincluding a first switch electrode coupled to said first photodiodeelectrode, a second switch electrode coupled to one of said plurality ofdata lines and a control electrode coupled to one of said plurality ofaddress lines; and capacitively coupling to at least one said firstphotodiode electrode with at least one electrode disposed substantiallyparallel with at least one portion of said plurality of pixels.
 10. Themethod of claim 9, wherein said capacitively coupling to at least onesaid first photodiode electrode with at least one electrode disposedsubstantially parallel with at least one portion of said plurality ofpixels comprises capacitively coupling with a plurality of planarconductors.
 11. The method of claim 9, wherein said capacitivelycoupling to at least one said first photodiode electrode with at leastone electrode disposed substantially parallel with at least one portionof said plurality of pixels comprises capacitively coupling with apatterned layer of electrically conductive material.
 12. The method ofclaim 9, wherein said capacitively coupling to at least one said firstphotodiode electrode with at least one electrode disposed substantiallyparallel with at least one portion of said plurality of pixels comprisescapacitively coupling with said at least one electrode disposed on atleast a portion of a layer of dielectric that is disposed over at leasta portion of said plurality of pixels.
 13. The method of claim 9,wherein said capacitively coupling to at least one said first photodiodeelectrode with at least one electrode disposed substantially parallelwith at least one portion of said plurality of pixels comprisescapacitively coupling with said at least one electrode disposed on atleast a portion of a substrate that is disposed under at least a portionof said plurality of pixels.
 14. The method of claim 9, wherein: saidcapacitively coupling to at least one said first photodiode electrodewith at least one electrode disposed substantially parallel with atleast one portion of said plurality of pixels comprises capacitivelycoupling with a plurality of electrodes disposed in an array; and saidmethod further comprises selectively conveying electrical charges fromone or more portions of said plurality of electrodes to receivingcircuitry.